Semiconductor memory devices have increasingly been used in a wide variety of electronic devices. Non-volatile semiconductor memory devices are now common in smart phones, tablet computers, personal digital assistants, digital cameras, audio recorders, digital video camcorders, and USB flash drives, to name a few. Such flash memory devices are among the most popular non-volatile semiconductor memories. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory element, such as a flash memory unit. Efforts of the semiconductor fabricating industry to produce continuing improvements in miniaturization and packing densities has seen improvements and new challenges in the semiconductor fabricating process.
Flash memory is typically made up of an array of floating gate transistors, commonly referred to as memory cells. One or more bits of data can be stored as charge by each memory cell. FIG. 1 illustrates an exemplary memory cell 100 utilizing a floating gate 102 that is positioned above and insulated from a channel region 104 in a semiconductor substrate 106. In one embodiment, the floating gate 102 is positioned between a first source/drain region 108 and a second source/drain region 110. A control gate 112 is placed over and insulated from the floating gate 102. A threshold voltage of the transistor is controlled by an amount of charge that is retained on its floating gate. The minimum amount of voltage that must be applied to the control gate 112 before conduction occurs between the first source/drain region 108 and the second source/drain region 110 is controlled by a level of charge on the floating gate 102. When conduction occurs between the first source/drain region 108 and the second source/drain region 110, the channel region 104 forms in the semiconductor substrate 106 between the first source/drain region 108 and the second source/drain region 110, and immediately beneath the floating gate 102.
FIG. 2 illustrates a typical two-dimensional array of floating gate memory transistors, or memory cells. FIG. 2 comprises several strings, known as NAND strings of floating gate memory transistors 210. Each transistor 210 of the NAND string is coupled to a next transistor 210 in the NAND string by coupling a source of one transistor 210 to a drain of a next transistor 210 to form bit lines BL1-BLn. Each NAND string illustrated in FIG. 2 includes a select transistor 212, 214 on either end of the string of memory cells. The drain side select transistor 212 connects the NAND strings to respective bit lines (BL1-BLn) and the source side select transistor 214 connects the NAND strings to a common source line 216. FIG. 2 also illustrates a plurality of word lines WL1-WLn running perpendicular to the NAND strings. As illustrated in FIG. 2, each word line (WL1-WLn) connects to the control gate 218 of one memory cell 210 of each NAND string.
In one embodiment, before programming a flash memory device, its memory cells are erased. In one embodiment, memory cells can be erased as part of a batch erase where all the memory cells existing in the memory cell array are erased at the same time. In another method, a memory device can be erased through a block erase, where a block consists of a group of NAND cells arranged in a row direction and sharing a common word line. As described herein, when a memory cell or a plurality of memory cells are erased, electrons are discharged into a semiconductor substrate from floating gates of the selected memory cells and threshold voltages of the selected memory cells are shifted in a negative direction.
In one embodiment, a flash memory device may be programmed by applying a program voltage to the control gate of the target memory cell and placing its bit line to ground. Electrons from the substrate channel may then be injected into the floating gate through a process known as tunneling. When electrons accumulate on the floating gate, the floating gate may become negatively charged and the threshold voltage of the memory cell raised so that the memory cell is in a programmed state. In the case of a NAND-type memory cell, the threshold voltages after data erase are normally “negative” and defined as “1.” The threshold voltages after data write are normally “positive” and defined as “0.”
When the threshold voltage is negative and a read is attempted, the memory cell will turn on; indicating logic “1” is stored. When the threshold voltage is positive and a read operation is attempted, the memory cell will not turn on; indicating logic “0” is stored. A memory cell can also store multiple bits of digital data, such as in exemplary Multi-Level Cell Architecture (MLC) devices. The range of possible threshold values may determine a number of possible levels of data. For example, if four levels of information are stored, there may be four threshold voltage ranges assigned to the data values “11,” “10,” “01,” and “00.” In one example of a NAND-type memory, the threshold voltage after an erasure may be negative and defined as “11.” In one embodiment, positive threshold voltages may be used for the states of “10,” “01,” and “00.”
When a memory cell is programmed (with a program signal), all of the memory cells on the same wordline may also receive the program signal. Even though the bit lines on their NAND strings are set to a supply voltage Vcc (e.g. 3-5 V), and inhibited, it may still be possible for another memory cell on the same wordline to be inadvertently programmed (e.g., disturbed). In particular, the memory cell adjacent to the memory cell selected for programming may be especially vulnerable to program disturb.
FIG. 2 illustrates a programmed memory cell S on a wordline WL3 along with inhibited memory cells Q on the same wordline WL3. As illustrated in FIG. 2, the selected bitline BL1 is set to ground and the inhibited bitlines B12-BLn are set to Vcc. The program signal Vpgm is applied to the selected wordline WL3 and is applied to the control gates 218 of the memory cells 210 along the wordline WL3 (e.g., memory cells S and Q). This places the program signal Vpgm on memory cells 210 in both the selected bitline BL1 (memory cell S) and the unselected bitlines BL2-BLn (memory cells Q). As discussed herein, the unintentional programming of an unselected memory cell Q on the selected wordline WL3 is called “program disturb.”
There have been many attempts to limit or prevent program disturb. Conventional self-boosting is an exemplary method whereby the unselected bitlines may be electrically isolated and a pass voltage applied to the unselected wordlines during programming. FIG. 3 illustrates conventional global self-boosting. A supply voltage Vcc (e.g. 3-5 V) is applied to both drains 302 and control gates 304 of the unselected drain side select transistors 212 to turn off the unselected drain side select transistors 212, and thereby electrically isolate the unselected bitlines. A pass voltage Vpass (e.g. 10 V) may be applied to the unselected wordlines (WL1, WL2, and WL4-WLn). The unselected wordlines (WL1, WL2, and WL4-WLn) capacitively couple to the unselected bitlines BL2-BLn, causing a voltage (such as about 6 volts) to exist in the channel of the unselected bit lines BL2-BLn, which may reduce program disturb. Self-boosting may reduce the potential difference between channels of the unselected bit lines BL2-BLn and the program signal Vpgm that is applied to the selected wordline WL3. The end result may be reduced voltage across the tunnel oxide and therefore reduced program disturb, especially in the memory cells Q in the unselected bitlines BL2-BLn on the selected wordline WL3.
However, conventional global self-boosting does have its disadvantages. A NAND string is typically programmed from the source side to the drain side. When all but the last few memory cells have been programmed, if all or most of the memory cells on the NAND string being inhibited were programmed, then there may be a negative charge in the floating gates of the previously programmed cells. Because of this negative charge on the floating gates, the boosting potential may not get high enough and there may still be program disturb on the last few wordlines. As illustrated in FIG. 4A, when programming one particular memory cell S, if memory cells B on a source side wordline and adjacent to inhibited memory cells Q on the selected wordline, were already programmed, the negative charge on their floating gates may limit the boosting level of the self-boosting process and possibly cause program disturb on the memory cell Q adjacent to the programmed memory cell S.
Conventional global self-boosting can also suffer from uneven channel voltage. In conventional global self-boosting, channel voltage may not be uniformly distributed if any cell in the string is programmed. Channel voltage on the drain side, with pre-charging, may be higher than the source side. That is, memory cells on the source side may be vulnerable to program disturbs. In other words, when there is non-uniform channel voltage, the voltage is different through the channel. The differences in channel voltage on either side of the programmed memory cell may continue to grow as more memory cells are programmed. Further, there is pattern dependent channel voltage, such that channel voltage may be different from bit line to bit line due to their varying programming/erasure patterns. The channel voltage is boosted in different amounts depending on the threshold voltages of the cells. As a result, when data is written into the selected memory cell in the selected NAND string, the stress due to the programming voltage applied to all the memory cells on the wordline may cause a disturbance in the previously programmed memory cells.